FR-LVDS-V/W
LVDS to DVI/VGA
LVDS TO VGA
- Converting input signals to TMDS with non-sync regulation
- VESA data format. (T3M&P for higher bit transmission)
- LVDS data latch at falling edge of transmit clock frequency of max. 85MHz.
- No EDID supported
FR-TTL-D/H
LVDS to DVI/VGA
TTL INPUT 18/ 24-BIT SIGNAL TO DVID OUTPUT
- Converting input signals to TMDS with non-sync regulation
- TTL-data latch at falling edge of pixel clock. (Max. TBD MHz)
- No EDID/ HDCP suppported
